The present invention generally relates to integrated circuit (IC) design, and more particularly, to verification of power management in an IC design.
Electronic circuits, such as microprocessors, microcontroller units (MCUs), system-on-chips (SoCs), and application specific integrated circuits (ASICs) are widely used in applications including industrial applications, automobiles, home appliances, and mobile and handheld devices. As an important safety critical example, SoCs are used to monitor and control critical functions in an automobile, such as opening of airbags. Power failure in SoCs can be fatal to the operation of the automobile and needs to be managed properly. Hence, power management plays a vital role in the operation of SoCs. An efficient power management system acts as a fail-safe mechanism against errors caused by power failures. Similarly, power management in other devices, such as mobile phones and laptop computers, is critical for the operation of these devices.
Power management systems are often integrated in SoCs by using low cost voltage regulators and board components to reduce the manufacturing cost. Low cost voltage regulator components often have poor bandwidth and hence are not reliable for high switching frequency SoCs. SoCs also may include heterogeneous cores and components that operate on mixed signals (both digital and analog). Signal noise and fluctuations caused due to changes in the activity of mixed signal components further result in additional demands on the power management systems to maintain a constant voltage in the SoCs.
Power management systems usually function satisfactorily under steady state conditions that include run and halt modes of a SoC. However, they are prone to failure in high demand situations that include load transitions and mode changes (transition of a SoC from run mode to halt mode and vice versa). The load on power management systems due to high demand situations, signal fluctuations, and constraints due to low cost components leads to power management problems. Conventional techniques identify these problems after the SoC design (including the power management system) has been transferred to a chip, thereby rendering further modifications difficult.
Therefore, there is a need for a power management system that functions efficiently with weak bandwidth voltage regulators and ensures safe operation against load transitions and mode changes of a SoC. Further, there is a need to verify power management systems, identify and rectify functional problems during the design stage of a SoC, i.e., before the power management system implemented in Silicon. Finally, there is a need for a power management system that overcomes the above-mentioned limitations of conventional power management systems.